CrystalCPUID is a CPU utility software. MSR Editor/MSR Walker; Clock, Cache, System Clock, Multiplier; Feature Flags; CPUID; Process Rule; Code Name. CrystalCPUID [Obsolete] CrystalCPUID is a CPU utility software. System Requirements OS x Vista//XP//NT4/Me/98/95 x Vista//XP IE advanced CPU utility Crystal CPUID is an advanced CPU identification utility that displays in-depth information about your processor(s).

If a software procedure can set and clear information information, the processor executing the information supports the Cpu instruction.

This instruction operates the same in nonbit modes and bit mode, CrystalCPUID – cpu information. Two types of CrystalCPUID are returned: basic and extended function information. EAX is higher than the maximum input value for basic or extended function for that processor then the data for the highest basic information leaf is returned.

EAX is less information or equal to the maximum input value and the leaf is not supported on that information then 0 is returned in all the registers. CPUID can be executed at any privilege level to serialize instruction execution. Serializing instruction execution guarantees cpu any modifications to flags, registers, and memory for previous instructions are completed before the next instruction is fetched and executed.

EBX Reserved. ECX Bits of bit processor serial number. Cpu in Pentium III processor cpu otherwise, the CrystalCPUID in this register is reserved, CrystalCPUID – cpu information. EDX Bits of bit processor serial number. Bits Cache Level starts at 1. Bit Self Initializing cache information does not need SW initialization.

Bit Fully Associative cache. Bits Reserved. Bit Cache Inclusiveness. Bit Complex Cache Indexing. Valid ECX values start from 0. EBX Bits Largest monitor-line size in bytes information is processor's monitor granularity, CrystalCPUID – cpu information.

Table Bit ARAT. APIC-Timer-always-running feature is supported if set. Bit Reserved. Bit PLN. Power limit notification controls are supported if information. Bit ECMD. Clock modulation duty cycle extension is supported if set. Bit PTM. Package thermal management is supported if set.

Bit HWP. Bit HDC. Bit HWP Capabilities. Highest Performance change is supported if set. Bit Flexible HWP is supported if set. The capability to provide a measure of delivered processor performance since last reset of the CrystalCPUIDas a percentage of the expected processor performance when running at the TSC frequency.

Information cpu that many classes is written into the Intel Thread Director Table by the hardware. Bits Index starting at 0 of this logical processor's row in the hardware feedback interface structure.

Note that on CrystalCPUID parts the index may be same for multiple logical processors. On some parts the indices may not be contiguous, CrystalCPUID. NOTE: Bits 0 and 1 cpu always be set together. CrystalCPUID SGX.

Bit BMI1. Bit HLE. Bit CrystalCPUID. Bit SMEP. Supports Supervisor-Mode Execution Prevention if 1, CrystalCPUID – cpu information. Bit BMI2. Bit RTM. Bit RDT-M, CrystalCPUID – cpu information. Bit MPX, CrystalCPUID – cpu information. Bit RDT-A. Bit AVXF. Bit ADX. Bit SMAP, CrystalCPUID – cpu information. Bit CLWB. Bit Intel Processor Trace. Bit SHA, CrystalCPUID – cpu information.

Bit UMIP. Supports user-mode instruction prevention CrystalCPUID 1. Bit PKU. Supports protection cpu for user-mode pages if 1. If 1, OS has set CR4. Supports CET shadow stack features if 1. Bit GFNI. Bit VAES. Bit LA Supports bit linear addresses and five-level paging if 1. Bit KL. Supports Key Locker if 1. If 1, indicates support for OS bus-lock detection. Supports cache line demote if 1. Supports Enqueue Stores if 1. Bit PKS. Supports protection cpu for supervisor-mode pages if 1, CrystalCPUID – cpu information.

EDX Bit Reserved. If 1, the processor supports user CrystalCPUID. Bit Hybrid. If 1, CrystalCPUID – cpu information, the processor is identified as a hybrid part. Bit Architectural LBRs. If 1, indicates support for architectural LBRs, CrystalCPUID – cpu information. Supports CET indirect branch information features if 1. CrystalCPUID 1, CrystalCPUID – cpu information, the processor supports tile cpu operations on bfloat16 numbers.

If 1, the processor supports tile architecture. If 1, the processor supports tile computational operations cpu 8-bit integers.

Sub-leaf index n is invalid if n exceeds cpu value that sub-leaf 0 returns in EAX. EAX This information reports 0 if the sub-leaf CrystalCPUID, 1, is information. If 1, CrystalCPUID – cpu information, these MSRs are supported. ECX This information reports 0 if the sub-leaf CrystalCPUID, 1, is invalid; otherwise it is reserved.

EDX This field reports 0 if the sub-leaf index, CrystalCPUID – cpu information, 1, is invalid. If 1, indicates that an operating system can enable supervisor shadow stacks as long as it ensures that certain supervisor shadow-stack pushes will not cause page faults see Section EAX This field reports 0 if the sub-leaf index, 2, is invalid; otherwise it is reserved.

EBX This field reports 0 if the sub-leaf index, 2, is invalid; otherwise it is reserved, CrystalCPUID – cpu information. ECX This field reports 0 if the sub-leaf index, cpu, is invalid; otherwise it is reserved.

EDX This field reports 0 if the sub-leaf index, 2, is invalid, CrystalCPUID – cpu information. Bit PSFD. ECX Reserved. EDX Reserved. Bits Number of cpu performance monitoring CrystalCPUID per logical processor.

Bits Bit width of general-purpose, performance monitoring counter.